Digantara is a leading Space Surveillance and Intelligence company focused on ensuring orbital safety and sustainability. With expertise in space-based detection, tracking, identification, and monitoring, Digantara provides comprehensive domain awareness across regimes, allowing end users to have actionable intelligence on a single platform. At the core of its infrastructure lies a sophisticated integration of hardware and software capabilities aligned with the key principles of situational awareness: perception (data collection), comprehension (data processing), and prediction (analytics). This holistic approach empowers Digantara to monitor all Resident Space Objects (RSOs) in orbit, fostering comprehensive domain awareness.

Digantara seeks an FPGA design Engineer to design and develop RTL modules for satellite payload electronics. The engineer will implement image processing algorithms and suitable data, control interfaces between the payload & the satellite bus.

Why Us?

Be part of a collaborative and innovative environment where your ideas and skills make a real difference to the entire space realm
Push the boundaries with hands-on experience, greater responsibilities, and rapid career advancement.
Competitive incentives, galvanising workspace, blazing team, frequent outings—pretty much everything that you have heard about a startup.

Ideal Candidate:

Someone with expertise in FPGA design for the satellite payload electronics/ground-based imaging systems.

Responsibilities:

Design and develop high-performance RTL modules for the FPGA-based payload electronics, to accomplish on-board image capture and processing.
Develop high-quality RTL and efficient custom IP blocks in VHDL/Verilog for AMD-Xilinx/Microchip FPGA target devices.
Implement high-speed interfaces with a processor such as SerDes, Gigabit Ethernet, PCIe, and AXI-4/AXI-4 Lite interface.
Carry out Synthesis, Place and Route, static timing analysis (STA), and close the timing requirements of the FPGA design.
Collaborate with hardware, embedded software, and image processing engineers to generate RTL design requirements, architecture, and test plans.
Document the FPGA design, verification, and validation, and board-level test results throughout the development lifecycle.

Required Qualifications:

B.Tech/B.E in Electronics Engineering or M.Tech/M.E or PhD in Microelectronics/Embedded systems/VLSI.
4 to 6 years of demonstrated experience in RTL design and development for FPGA-based digital systems.
Strong proficiency in VHDL/Verilog-based digital logic implementation with expertise in FPGA design flow using Vivado/Libero EDA tools.
Deep understanding of FPGA architecture, Synthesis, and Static Timing Analysis, Clock domain crossing techniques, and timing closure.
Strong expertise in troubleshooting logical and timing observations during the development lifecycle.
Proficiency in working with FPGA/SoC development kits and electronic test equipment.

Preferred Skills:

Familiarity with digital image processing and image compression implementation on an FPGA.
Experience in developing reliable and robust FPGA designs for satellite payloads is a significant plus.
Experience with Questasim or similar tools for functional verification and code coverage analysis.
Knowledge of Embedded software development in C/C++ and algorithm implementation in MATLAB/Python.
Knowledge of the latest advancements in FPGA-based payload electronics development.
Familiarity with the standards for satellite hardware development is an advantage.

General Requirements

Ability to work in a mission-focused, operational environment.
Ability to think critically and make independent decisions.
Interpersonal skills to enable working in a diverse and dynamic team.
Maintain a regular and predictable work schedule.
Writing and delivering technical documents and briefings.
Verbal and written communications skills as well as organizational skills.
Travel occasionally as necessary.

Job Location: Hebbal, Bengaluru.